by PeterJ.Ashenden (Author)
A guide to VHDL for digital system modeling. It aims to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification.
Format: Illustrated
Pages: 528
Edition: 2
Publisher: Morgan Kaufmann
Published: 19 May 2008
ISBN 10: 1558608656
ISBN 13: 9781558608658