by SanjayChuriwala (Author), SapanGarg (Author)
This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.
Format: Hardcover
Pages: 220
Edition: 1st Edition.
Publisher: Springer
Published: 08 May 2011
ISBN 10: 1441992952
ISBN 13: 9781441992956