Design Cost-efficient Interconnect Processing Units (System-on-chip Design and Technologies): The Spidergon STNoC

Design Cost-efficient Interconnect Processing Units (System-on-chip Design and Technologies): The Spidergon STNoC

by Marcello Coppola (Author), Miltos D . Grammatikakis (Author), Lorenzo Pieralisi (Author), Giuseppe Maruccia (Author), RiccardoLocatelli (Author)

Synopsis

Examines the technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. This book shows how the System-on-Chip and Network-on-Chip technology works why developers designed it the way they did the system-level design methodology.

$121.34

Quantity

5 in stock

More Information

Format: Hardcover
Pages: 288
Edition: 1
Publisher: CRC Press
Published: 17 Sep 2008

ISBN 10: 1420044710
ISBN 13: 9781420044713