System-on-Chip Test Architectures: Nanometer Design for Testability: Volume . (Systems on Silicon)

by Laung-Terng Wang (Author)

• New

  Illustrated
  2008

  $66.27

  A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.